1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to computer automated methods for designing support pillar masks used in fabricating air dielectric interconnect structures.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor ("MOS") devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices such as MOS transistors.
Conventionally, a dielectric layer is deposited over the devices and via holes are formed through the dielectric layer to the devices below. After the via holes are etched through the dielectric layer, a metallization layer is deposited over the dielectric surface filling the via holes to define metal filled vias. After the first metallization layer has been deposited, it is patterned to form interconnect metallization lines. As is well known in the art, "patterning" may be accomplished by depositing a photoresist layer, selectively exposing the photoresist to light, developing the photoresist to form an etch mask, and etching the exposed metallization to pattern the metallization layer, and removing the etch mask. This process may then be repeated if additional layers of metallization lines are desired.
As the demand for faster, more complex and compact IC chips increases, the performance of the interconnects has become increasingly important. Although individual transistor speeds have continued to improve by implementing shorter gate lengths and less resistive gate electrodes, improvements in interconnect structure speed has lagged.
As is well known in the art, the speed of interconnect structures is generally characterized in terms of RC delays (i.e., resistance/capacitance timing delays). Therefore, efforts at reducing RC delays in interconnect structures have involved experimentation with dielectric materials to reduce capacitance and with metals to reduce resistance. As is well known in the art, different metals have different resistivities, and each have different IC fabrication benefits and drawbacks. By way of example, the resistance of copper (Cu) and silver (Ag) are relatively lower than aluminum (Al), but these metals are known to be more susceptible to corrosion. In addition, lowering the resistance of metal interconnect lines typically does not result in as great a benefit as reducing interconnect capacitance since all metals have relatively low resistance.
As is well known in the art, the capacitance associated with an interconnect structure is directly proportional to the dielectric constant (.epsilon..sub.o) of the dielectric layer lying between the "plates" of the capacitor, i.e., adjacent metallization layers (i.e., C .alpha. .epsilon..sub.o). Therefore, interconnect capacitance may be reduced by lowering the dielectric constant of the material lying between metallization lines. Conventionally, silicon dioxide having a dielectric constant of about 4.0 is used to isolate the various interconnect metallization lines in IC chips. However, there have been various unsuccessful attempts at reducing capacitance by developing low dielectric materials. Such materials include organic-type dielectrics which have dielectric constants between about 2.0 and 4.0.
Unfortunately, the use of organic-type dielectrics present various fabrication difficulties. By way of example, fabrication difficulties may include excessive moisture uptake, increased susceptibility to sodium contamination, and a lack of global planarization schemes available to planarize organic-type dielectric materials. As a result, many IC manufactures avoid excessive cost and time consuming fabrication processes associated with organic-type dielectrics.
Air has a dielectric constant of about 1.0. Although it is well known that air has a low dielectric constant, there are significant difficulties associated with constructing multi-level interconnect structures utilizing air as a dielectric, including the complex task of providing mechanical support for stacked metallization layers during fabrication. As a result, in the past, fabricating interconnect structures with air as a dielectric (if at all possible) was prohibitively expensive as compared to the benefits of increased circuit speeds attributed to low dielectric constants.
FIGS. 1A and 1B represent a cross-sectional view and a top view, respectively of a prior art interconnect structure 12 having a suspended portion 14 over a silicon substrate 10. For a more detailed description of the steps associated with fabricating this prior art interconnect structure, reference may be made to a paper entitled "VLSI Multilevel Micro-Coaxial Interconnects for High Speed Devices" by M. E. Thomas, et al., Fairchild Research Center, National Semiconductor Corporation, Santa Clara, Calif., IEDM Tech. Dig., pages 55-58 (1990), which is hereby incorporated by reference. Interconnect structure 12 includes an inner conductor 20, a insulating dielectric coating 18 and an outer conductive layer 16 that serves to encapsulate the insulating dielectric coating 18. Interconnect structure 12 also includes two contact posts 13 fabricated to have a larger dimension so as to support suspended portion 14.
It should be noted that the suspended portion 14 tends to sag under the influence of gravity. Therefore, there is a limit to the suspended length of such structures before they fracture and break, which is a significant practical problem in implementing this prior art structure. Another problem encountered with the interconnect structure of FIG. 1A is the inability to stack multiple interconnect layers. By way of example, if a second interconnect structures were built over structure 12, the probability of breaking center region 14 dramatically increases due to the lack of mechanical support under center region 14.
Although the benefits of using air as a dielectric for interconnect structures is well known, most designers still avoid air as the dielectric in densely integrated devices because the special masks used for designing "pillars" that support the thousands or sometimes millions of suspended interconnect lines can be a very labor intensive task that is often times prohibitively expensive. By way of example, a current technique used for laying out the multitude of interconnect lines needed to complete the transistor interconnections in an application specific integrated circuit (ASIC), is to utilize well known "place and route" software tools.
This is especially useful in gate array masterslice devices where thousands of identical base cells, each having a standard transistor pattern, need many interconnect lines to complete the ASIC device. Once the "place and route" software tool designs the interconnect lines needed to complete the ASIC device, if air is desired as the dielectric, designers are generally required to manually design special masks used to fabricate the support pillars to mechanically support the suspended interconnect lines at various locations. Unfortunately, for large scale ASIC devices, the number of suspended interconnect lines may number in the thousands or millions. As a result, most designers are typically required to spend many months studying and inspecting the interconnect line layouts to determine the appropriate locations for the thousands or millions of support pillars needed in an air dielectric interconnect structure.
In view of the foregoing, what is needed is a computer an automated method and apparatus for designing interconnect mask layouts for fabricating support pillars used to mechanically support air dielectric interconnect structures.